1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, it relates to a method of fabricating a semiconductor device having an element isolation trench.
2. Description of the Prior Art
In recent years, further reduction of a design rule is studied in order to improve the degree of integration and the speed of a semiconductor device. At present, prototypes of a 256-M DRAM (Dynamic Random Access Memory) and a CMOS (Complementary Metal Oxide Semiconductor) transistor having a gate length of 0.1 xcexcm are opened to the public. Following such progress of refinement of the transistor, reduction of the device size according to a scaling law and following increase of the operating speed are expected.
In relation to miniaturization of the device, it is extremely important to improve an element isolation technique for isolating refined transistors from each other in addition to refinement of the transistor.
In general, the LOCOS (local oxidation of silicon) method is employed for element isolation. In the LOCOS method, however, the element isolation width cannot be sufficiently reduced due to lateral spreading (bird""s beak) of a silicon oxide film for isolating elements from each other by oxidation isolation.
To this end, STI (shallow trench isolation) of forming a trench for element isolation between elements and embedding a silicon oxide film in the trench thereby isolating the elements from each other is proposed.
When STI is employed, the element isolation width is not limited by a bird""s beak dissimilarly to the LOCOS method, whereby the device can be further refined.
When STI is employed, however, an upper corner portion of the trench is sharply shaped as compared with that in the LOCOS method. When a transistor is fabricated, therefore, an electric field from a gate electrode to a channel region concentrates on the upper corner portion of the trench, to disadvantageously reduce a threshold voltage in the upper corner portion of the trench. Further, a leakage current disadvantageously readily flows through the portion having the reduced threshold voltage.
A method of suppressing field concentration on the upper corner portion of the trench by rounding this upper corner portion is known as a method of avoiding the aforementioned problems caused in the STI. Also when reduction of the threshold voltage caused by field concentration is suppressed, however, the threshold voltage disadvantageously fluctuates due to diffusion of an impurity in the upper corner portion of the trench. In an nMOSFET, for example, boron serving as a p-type impurity is generally implanted into a channel region. This boron diffuses out toward a silicon oxide film embedded in the trench and a silicon oxide film formed by rounding the upper corner portion of the trench, and hence the boron concentration is reduced in the upper corner portion of the trench. Consequently, the threshold voltage is partially reduced in the upper corner portion of the trench.
For example, Japanese Patent Laying-Open No. 2000-150878 discloses a technique for suppressing reduction of a threshold voltage resulting from diffusion of an impurity. In a method of fabricating a semiconductor device proposed in this gazette, a trench for element isolation is first formed on a semiconductor substrate. An impurity of the same conductivity type as that for forming a channel region is obliquely ion-implanted into the main surface of the semiconductor substrate. Thus, the impurity sufficiently remains in the edge of the channel region (the upper corner portion of the trench) even upon out diffusion of the impurity, and hence reduction of the threshold voltage can be suppressed.
However, this proposed technique has the following problems:
Consider that the aforementioned proposed technique is applied to a CMOS transistor having a first conductivity type channel region and a second conductivity type channel region on a substrate. In this case, when the first conductivity type impurity is ion-implanted into the first conductivity type channel region, an ion implantation mask such as a resist mask must be formed on the second conductivity type channel region, in order to ion-implant impurities of the same conductivity types as the channel regions.
However, an end of the ion implantation mask blocks the impurity when the same is obliquely implanted into the channel region located on the inner side surface of the trench through the ion implantation mask. Thus, it is difficult to sufficiently implant the impurity into the channel region. In other words, it is difficult to implant the impurity into the channel region when the ion implantation mask shades the channel region. Particularly when elements are refined, the end of the ion implantation mask so approaches the channel region subjected to ion implantation that the channel region is readily shaded by the ion implantation mask.
The impurity may alternatively be implanted into the overall surface of the trench without through the ion implantation mask. However, when first conductivity type impurity ions are implanted into the overall surface of the trench in order to suppress reduction of the threshold voltage caused by diffusion of the impurity in the upper corner portion of the first conductivity type channel region, for example, the first conductivity type impurity is inevitably also implanted into the second conductivity type channel region. In the upper corner portion of the second conductivity type channel region, therefore, the action of the impurity is canceled and the threshold voltage is reduced. Consequently, a leakage current disadvantageously readily flows through the portion having the reduced threshold voltage.
As hereinabove described, it is generally difficult to suppress fluctuation of the threshold voltage in the upper corner potion of the trench isolating the first conductivity type channel region and the second conductivity type channel region from each other.
An object of the present invention is to provide a method of fabricating a semiconductor device capable of suppressing fluctuation of a threshold voltage in an upper corner portion of a trench isolating a first conductivity type channel region and a second conductivity type channel region from each other.
Another object of the present invention is to reliably introduce a first impurity into the upper corner portion of the trench in the aforementioned method of fabricating a semiconductor device.
A method according to a first aspect of the present invention is a method of fabricating a semiconductor device including a first transistor having a first conductivity type channel region and a second transistor having a second conductivity type channel region, comprising steps of forming a trench for isolating the first transistor and the second transistor from each other on a semiconductor substrate, rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench, introducing a second impurity into a region for defining the first conductivity type channel region, introducing a third impurity into a region for defining the second conductivity type channel region and heat-treating the semiconductor substrate. According to the present invention, the term xe2x80x9csemiconductor substratexe2x80x9d indicates a wide concept including not only an ordinary semiconductor substrate but also a semiconductor layer formed on an insulating substrate or the like.
In the method of fabricating a semiconductor device according to the first aspect, the first impurity is introduced into both upper corner portions of the trench after rounding the upper corner portions of the trench by thermal oxidation as described above, whereby the threshold voltage in the upper corner potion of the trench can be previously increased by rounding oxidation and introduction of a p-type impurity in an n-channel transistor when employing the p-type impurity as the first impurity, for example. Reduction of the threshold voltage in the upper corner portion of the trench resulting from diffusion of an impurity for heat-treating the semiconductor substrate can be canceled due to this increase of the threshold voltage. In the n-channel transistor, therefore, the threshold voltage can be effectively inhibited from fluctuation in the upper corner portion of the trench. Consequently, it is possible to suppress increase of a leakage current caused by reduction of the threshold voltage of the n-channel transistor in the upper corner portion of the trench.
In a p-channel transistor, the threshold voltage in the upper corner portion of the trench can be previously increased by rounding oxidation. Thus, it is possible to cancel reduction of the threshold voltage caused by introducing the p-type first impurity into both upper corner portions of the trench, whereby the threshold voltage can be effectively inhibited from fluctuation in the upper corner portion of the trench. Consequently, it is possible to suppress increase of a leakage current caused by reduction of the threshold voltage of the p-channel transistor in the upper corner potion of the trench.
Further, the first impurity is introduced into both upper corner portions of the trench so that the region subjected to ion implantation may not be limited through an ion implantation mask such as a resist mask, whereby no region is shaded by such an ion implantation mask when the first impurity is introduced. Thus, the first impurity can be reliably introduced into both upper corner portions of the trench. Further, no step of forming an ion implantation mask is necessary, whereby the fabrication process can be simplified.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of forming the trench preferably includes steps of forming a first mask layer on a prescribed region of the semiconductor substrate and forming the trench by etching the semiconductor substrate through the first mask layer serving as a mask, and the step of introducing the first impurity preferably includes a step of introducing the first impurity into both upper corner portions of the trench while leaving the first mask layer. According to this structure, the first impurity can be prevented from being implanted into regions other than ends (the upper corner portions of the trench) of channel regions.
In this case, the step of introducing the first impurity preferably includes a step of implanting the first impurity into both upper corner portions of the trench obliquely to the main surface of the semiconductor substrate while leaving the first mask layer. According to this structure, the first impurity can be readily implanted into the upper corner potions of the trench. In this case, the first mask layer preferably includes a silicon nitride film.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of introducing the first impurity preferably includes a step of implanting the first impurity into both upper corner portions of the trench with implantation energy for locating a peak of impurity concentration in the vicinity of the surface of the semiconductor substrate. According to this structure, the first impurity can be readily prevented from being implanted into central portions of the channel regions.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the first impurity introduced into both upper corner portions of the trench may include boron.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of forming the trench preferably includes steps of forming a first mask layer on a prescribed region of the semiconductor substrate and forming the trench by etching the semiconductor substrate through the first mask layer serving as a mask, and the method preferably further comprises a step of forming an insulator in the trench and on the semiconductor substrate and thereafter polishing the upper surface of the insulator through the first mask layer serving as a stopper thereby embedding the insulator in the trench. According to this structure, the insulator can be readily embedded in the trench.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of heat-treating the semiconductor substrate preferably includes a step of heat-treating the semiconductor substrate at a temperature of about 700xc2x0 C. to about 1100xc2x0 C. In this case, the step of heat-treating the semiconductor substrate preferably includes a step of performing heat treatment by rapid heating. According to this structure, the impurity can be readily activated by this heat treatment.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of rounding the upper corner portions of the trench preferably includes a step of rounding the upper corner portions of the trench by forming a thermal oxide film of about 50 nm to about 600 nm at a temperature of about 1000xc2x0 C. to about 1200xc2x0 C. When the heat treatment is performed under such conditions, the upper corner portions of the trench can be sufficiently rounded.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the second impurity preferably includes boron, and the third impurity preferably includes arsenic or phosphorus.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of introducing the second impurity into the region for defining the first conductivity type channel region preferably includes steps of forming a second mask layer to cover a region formed with the second transistor having the second conductivity type channel region and implanting the second impurity into the region for defining the first conductivity channel region through the second mask layer serving as a mask. According to this structure, the second impurity can be implanted only into the region for defining the first conductivity type channel region.
In the method of fabricating a semiconductor device according to the aforementioned first aspect, the step of introducing the third impurity into the region for defining the second conductivity type channel region preferably includes steps of forming a third mask layer to cover a region formed with the first transistor having the first conductivity type channel region and implanting the third impurity into the region for defining the second conductivity type channel region through the third mask layer serving as a mask. According to this structure, the third impurity can be implanted only into the region for defining the second conductivity type channel region.
A method according to a second aspect of the present invention is a method of fabricating a semiconductor device including a first transistor having a first conductivity type channel region and a second transistor having a second conductivity type channel region, comprising steps of successively depositing a silicon oxide film and a silicon nitride film on a semiconductor substrate, forming a resist mask on a prescribed region of the silicon nitride film, patterning the silicon nitride film and the silicon oxide film through the resist mask, forming a trench for isolating the first transistor and the second transistor from each other by etching the semiconductor substrate through the patterned silicon nitride film serving as a mask, rounding upper corner portions of the trench by thermal oxidation, implanting a first impurity into both upper corner portions of the trench through the silicon nitride film serving as a mask, introducing a second impurity into a region for defining the first conductivity channel region, introducing a third impurity into a region for defining the second conductivity type channel region and heat-treating the semiconductor substrate.
In the method of fabricating a semiconductor device according to the second aspect, the first impurity is introduced into both upper corner portions of the trench after rounding the upper corner portions of the trench by thermal oxidation as described above, whereby the threshold voltage in the upper corner potion of the trench can be previously increased by rounding oxidation and introduction of a p-type impurity in an n-channel transistor when employing the p-type impurity as the first impurity, for example. Reduction of the threshold voltage in the upper corner portion of the trench resulting from diffusion of an impurity for heat-treating the semiconductor substrate can be canceled due to this increase of the threshold voltage. In the n-channel transistor, therefore, the threshold voltage can be effectively inhibited from fluctuation in the upper corner portion of the trench. Consequently, it is possible to suppress increase of a leakage current caused by reduction of the threshold voltage of the n-channel transistor in the upper corner portion of the trench.
In a p-channel transistor, the threshold voltage in the upper corner portion of the trench can be previously increased by rounding oxidation. Thus, it is possible to cancel reduction of the threshold voltage caused by introducing the p-type first impurity into the upper corner portions of the trench, whereby the threshold voltage can be effectively inhibited from fluctuation in the upper corner portion of the trench. Consequently, it is possible to suppress increase of a leakage current caused by reduction of the threshold voltage of the p-channel transistor in the upper corner potion of the trench.
Further, the first impurity is introduced into both upper corner portions of the trench so that the region subjected to ion implantation may not be limited through an ion implantation mask such as a resist mask, whereby no region is shaded by such an ion implantation mask when the first impurity is introduced. Thus, the first impurity can be reliably introduced into both upper corner portions of the trench.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.